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lt6016/lt6017 1 60167fa typical application features description dual/quad 3.2mhz, 0.8v/s low power, over-the-top precision op amp applications l , lt, ltc, ltm, linear technology, over-the-top and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n input common mode range: v C to v C + 76v n rail-to-rail input and output n low power: 315a/amplifier n operating temperature range: C55c to 150c n v os : 50v (maximum) n cmrr, psrr: 126db n reverse battery protection to 50v n gain bandwidth product: 3.2mhz n specified on 5v and 15v supplies n high voltage gain: 1000v/mv n no phase reversal n no supply sequencing problems n dual 8-lead msop n quad 22-lead dfn (6mm 3mm) n high side or low side current sensing n battery/power supply monitoring n 4ma to 20ma transmitters n high voltage data acquisition n battery/portable instrumentation the lt ? 6016/lt6017 are dual and quad rail-to-rail input operational amplifiers with input offset voltage trimmed to less than 50v. these amplifiers operate on single and split supplies with a total voltage of 3v to 50v and draw only 315a per amplifier. they are reverse battery protected, drawing very little current for reverse supplies up to 50v. the over-the-top ? input stage of the lt6016/lt6017 is de- signed to provide added protection in tough environments. the input common mode range extends from v C to v + and beyond: these amplifiers operate with inputs up to 76v above v C independent of v + . internal resistors protect the inputs against transient faults up to 25v below the negative supply. the lt6016/lt6017 can drive loads up to 25ma and are unity-gain stable with capacitive loads as large as 200pf. optional external compensation can be added to extend the capacitive drive capability beyond 200pf. the lt6016 dual op amp is available in an 8-lead msop package. the lt6017 is offered in a 22-pin leadless dfn package. precision high voltage high side load current monitor output error vs load current C + lt6016 5v 0.1f 200 100 1% 200 0.1 10w bsp89 1v/a 0v to 1v out v bat = 1.5v to 76v 60167 ta01a 2k load load current (a) 0.01 C1.0 output error (%) 0 0.2 C0.2 C0.4 C0.6 C0.8 0.1 60167 ta01b 1 v bat = 1.5v v bat = 5v v bat = 20v v bat = 75v
lt6016/lt6017 2 60167fa pin configuration absolute maximum ratings (note 1) 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 outd ?ind +ind n/c v + n/c v + n/c +inc ?inc outc outa ?ina +ina n/c v ? n/c v ? n/c +inb ?inb outb top view 23 djc package 22-lead (6mm 3mm) plastic dfn b c a d t jmax = 150c,
lt6016/lt6017 3 60167fa electrical characteristics symbol parameter conditions min i-, h-grade typ max units v os input offset voltage 0 < v cm < v + C 1.75v ms8 package 0 < v cm < v + C 1.75v djc22 package v cm = 5v v cm =76v 0 < v cm < v + C 1.75v v cm = 5v to v cm = 76v l l C50 C80 C125 C135 C250 C350 25 45 50 50 45 50 50 80 125 135 250 350 v v v v v v v v os temp input offset voltage drift 0.75 v/c v os time long term voltage offset stability 0.75 v/mo i b input bias current 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v v s = 0v, v cm = 0v to 76v l l l l C5 C30 11 C15 C150 7 2 C16.5 14 2 C16.5 14 0.001 5 0 17.5 15 0 23 1 na na a na na a a i os input offset current 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v (note 6) 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v (note 6) l l l C5 C5 C500 C15 C15 C500 2 2 50 2 2 50 5 5 500 15 15 500 na na na na na na vcmr common mode input range l 076v c in differential input capacitance 5pf r in differential input resistance 0 < v cm < v + C 1.75v v cm > v + 1 3.7 m k r incm common mode input resistance 0 < v cm < v + C 1.75v v cm > v + >1 >100 g m e n input referred noise voltage density f = 1khz v cm < v + C 1.75v v cm > v + 18 25 nv/ hz nv/ hz input referred noise voltage f = 0.1hz to 10hz v cm < v + C 1.75v 0.5 v p-p i n input referred noise current density f = 1khz v cm < v + C 1.75v v cm > v + 0.1 11.5 pa/ hz pa/ hz a vol open loop gain r l = 10k v out = 3v l 300 3000 v/mv psrr supply rejection ratio v s = 1.65v to 15v v cm = v out = mid-supply l 110 126 db cmrr input common mode rejection ratio v cm = 0v to 3.25v v cm = 5v to 76v l l 100 126 126 140 db db v ol output voltage swing low v s = 5v, no load v s = 5v, 5ma l l 3 280 55 500 mv mv v oh output voltage swing high v s = 5v, no load v s = 5v, 5ma l l 450 1000 700 1250 mv mv i sc short-circuit current v s = 5v, 50 to v + v s = 5v, 50 to v C l l 10 10 25 25 ma ma the l denotes the specifications which apply over the specified temperature range, C40c < t a < 85c for i-grade parts, C40c < t a < 125c for hCgrade parts, otherwise specifications are at t a = 25c, v s = 5v, v cm = v out = mid-supply.
lt6016/lt6017 4 60167fa electrical characteristics the l denotes the specifications which apply over the specified temperature range, C40c < t a < 85c for i-grade parts, C40c < t a < 125c for hCgrade parts, otherwise specifications are at t a = 25c, v s = 5v, v cm = v out = mid-supply. symbol parameter conditions min i-, h-grade typ max units v osi input offset voltage v s = 25v v s = 25v l l C80 C250 C110 C250 55 55 75 75 80 250 110 250 v v v v v osi temp input offset voltage drift 0.75 v/c i b input bias current l C5 C15 2 2 5 15 na na i os input offset current l C5 C15 2 2 5 15 na na vcmr common mode input range l C15 61 v c in differential input capacitance 5pf r in differential input resistance 0 < v cm < v + C 1.75v v cm > v + 1 3.7 m k r incm common mode input resistance 0 < v cm < v + C 1.75v v cm > v + >1 >100 g m e n input referred noise voltage density f = 1khz v cm < v + C 1.75v v cm > v + 18 25 nv/ hz nv/ hz input referred noise voltage f = 0.1hz to 10hz v cm < v + C 1.25v 0.5 v p-p i n input referred noise current density f = 1khz v cm < v + C 1.75v v cm > v + 0.1 11.5 pa/ hz pa/ hz a vol open loop gain r l = 10k v out = 27v l 200 1000 v/mv psrr supply rejection ratio v s = 2.5v to 25v v cm = v out = 0v l 114 126 db cmrr input common mode rejection ratio v cm = C15v to 13.25v l 110 126 db v ol output voltage swing low v s = 15v, no load v s = 15v, 5ma l l 3 280 55 500 mv mv v oh output voltage swing high v s = 15v, no load v s = 15v, 5ma l l 450 1000 700 1250 mv mv the l denotes the specifications which apply over the specified temperature range, C40c < t a < 85c for i-grade parts, C40c < t a < 125c for hCgrade parts, otherwise specifications are at t a = 25c, v s = 15v, v cm = v out = mid-supply. symbol parameter conditions min i-, h-grade typ max units gbw gain bandwidth products f test = 10khz l 2.85 2.5 3.2 3.2 mhz mhz sr slew rate v out = 3v l 0.55 0.45 0.75 0.75 v/s v/s t s settling time due to input step v out = 2v 0.1% settling 3.5 s v s supply voltage reverse supply (note 7) i s < C25a/amplifier l l 3 3.3 C65 50 50 C50 v v v i s supply current per amplifier v s = 5v l 315 315 335 500 a a r o output impedance i o = 5ma 0.15
lt6016/lt6017 5 60167fa electrical characteristics the l denotes the specifications which apply over the specified temperature range, C40c < t a < 85c for i-grade parts, C40c < t a < 125c for hCgrade parts, otherwise specifications are at t a = 25c, v s = 15v, v cm = v out = mid-supply. symbol parameter conditions min mp-grade typ max units v os input offset voltage 0 < v cm < v + C 1.75v ms8 package 0 < v cm < v + C 1.75v djc22 package v cm = 5v v cm = 76v 0 < v cm < v + C1.75v v cm = 5v to v cm = 76v l l C50 C80 C125 C135 C500 C600 25 45 50 50 45 50 50 80 125 135 500 600 v v v v v v v v os temp input offset voltage drift 0.75 v/c v os time long term voltage offset stability 0.75 v/mo i b input bias current 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v v s = 0v, v cm = 0v to 76v l l l l C5 C30 11 C100 C500 6.5 2 C16.5 14 2 C16.5 14 0.001 5 0 17.5 100 0 24 4 na na a na na a a i os input offset current 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v (note 6) 0.25v < v cm < v + C 1.75v v cm = 0v v cm = 5v to 76v (note 6) l l l C5 C5 C500 C50 C200 C500 2 2 50 2 2 150 5 5 500 50 200 500 na na na na na na vcmr common mode input range l 076v c in differential input capacitance 5pf r in differential input resistance 0 < v cm < v + C 1.75v v cm > v + 1 3.7 m k r incm common mode input resistance 0 < v cm < v + C 1.75v v cm > v + >1 >100 g m the l denotes the specifications which apply over the specified temperature range, C55c < t junction < 150c for mp-grade parts, otherwise specifications are at t a = 25c, v s = 5v, v cm = v out = mid-supply. symbol parameter conditions min i-, h-grade typ max units i sc short-circuit current v s = 15v, 50 to gnd v s = 15v, 50 to gnd l l 10 10 30 32 ma ma gbw gain bandwidth product f test = 10khz l 2.9 2.55 3.3 3.3 mhz mhz sr slew rate v out = 3v l 0.6 0.5 0.8 0.8 v/s v/s t s settling time due to input step 0.1% settling v out = 2v 3.5 s v s supply voltage reverse supply i s = C25a/amplifier l l 3 3.3 C65 50 50 C30 v v v i s supply current per amplifier v s = 25v v s = 25v l l 325 325 340 340 350 525 360 550 a a a a r o output impedance i o = 5ma 0.15
lt6016/lt6017 6 60167fa electrical characteristics the l denotes the specifications which apply over the specified temperature range, C55c < t junction < 150c for mp-grade parts, otherwise specifications are at t a = 25c, v s = 5v, v cm = v out = mid-supply. symbol parameter conditions min mp-grade typ max units v osi input offset voltage v s = 25v v s = 25v l l C80 C500 C110 C500 55 55 75 75 80 500 110 500 v v v v v osi temp input offset voltage drift 0.75 v/c i b input bias current l C5 C300 2 2 5 300 na na i os input offset current l C5 C50 2 2 5 50 na na vcmr common mode input range l C15 61 v c in differential input capacitance 5pf r in differential input resistance 0 < v cm < v + C 1.75v v cm > v + 1 3.7 m k the l denotes the specifications which apply over the specified t emperature range, C55c < t junction < 150c for mp-grade parts, otherwise specifications are at t a = 25c, v s = 15v, v cm = v out = mid-supply. symbol parameter conditions min mp-grade typ max units e n input referred noise voltage density f = 1khz v cm < v + C 1.75v v cm > v + 18 25 nv/ hz nv/ hz input referred noise voltage f = 0.1hz to 10hz v cm < v + C 1.75v 0.5 v p-p i n input referred noise current density f = 1khz v cm < v + C 1.75v v cm > v + 0.1 11.5 pa/ hz pa/ hz a vol open loop gain r l = 10k v out = 3v l 200 3000 v/mv psrr supply rejection ratio v s = 1.65v to 15v v cm = v out = mid-supply l 106 126 db cmrr input common mode rejection ratio v cm = 0v to 3.25v v cm = 5v to 76v l l 90 120 126 140 db db v ol output voltage swing low v s = 5v, no load v s = 5v, 5ma l l 3 280 75 550 mv mv v oh output voltage swing high v s = 5v, no load v s = 5v, 5ma l l 450 1000 750 1300 mv mv i sc short-circuit current v s = 5v, 50 to v + v s = 5v, 50 to v C l l 8 8 25 25 ma ma gbw gain bandwidth product f test = 10khz l 2.85 2.4 3.2 3.2 mhz mhz sr slew rate v out = 3v l 0.55 0.4 0.75 0.75 v/s v/s t s settling time due to input step 0.1% settling v out = 2v 3.5 s v s supply voltage reverse supply (note 7) i s < C25va/amplifier l l 3 3.3 C63 50 50 C50 v v v i s supply current per amplifier v s = 5v l 315 315 335 540 a a r o output impedance i o = 5ma 0.15
lt6016/lt6017 7 60167fa the l denotes the specifications which apply over the specified temperature range, C55c < t junction < 150c for mp-grade parts, otherwise specifications are at t a = 25c, v s = 15v, v cm = v out = mid-supply. electrical characteristics symbol parameter conditions min mp-grade typ max units r incm common mode input resistance 0 < v cm < v + C 1.75v v cm > v + >1 >100 g m e n input referred noise voltage density f = 1khz v cm < v + C 1.75v v cm > v + 18 25 nv/ hz nv/ hz input referred noise voltage f = 0.1hz to 10hz v cm < v + C 1.75v 0.5 v p-p i n input referred noise current density f = 1khz v cm < v + C 1.75v v cm > v + 0.1 11.5 pa/ hz pa/ hz a vol open loop gain r l = 10k v out = 27v l 100 1000 v/mv psrr supply rejection ratio v s = 2.5v to 25v v cm = v out = 0v l 106 126 db cmrr input common mode rejection ratio v cm = C15v to 13.25v l 100 126 db v ol output voltage swing low v s = 15v, no load v s = 15v, 5ma l l 3 280 75 550 mv mv v oh output voltage swing high v s = 15v, no load v s = 15v, 5ma l l 450 1000 750 1300 mv mv i sc short-circuit current v s = 15v, 50 to gnd v s = 15v, 50 to gnd l l 8 8 30 32 ma ma gbw gain bandwidth product f test = 10khz l 2.9 2.45 3.3 3.3 mhz mhz sr slew rate v out = 3v l 0.6 0.45 0.8 0.8 v/s v/s t s settling time due to input step 0.1% settling v out = 2v 3.5 s v s supply voltage reverse supply i s = C25a/amplifier l l 3 3.3 C65 50 50 C30 v v v i s supply current per amplifier v s = 25v v s = 25v l l 325 325 340 340 350 575 360 600 a a a a r o output impedance i o = 5ma 0.15 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: voltages applied are with respect to v C . the inputs are tested to the absolute maximum rating by applying C25v (relative to v C ) to each input for 10ms. in general, faults capable of sinking current from either input should be current limited to under 10ma. see the applications information section for more details. note 3: a heat sink may be required to keep the junction temperature below absolute maximum. this depends on the power supply voltage and how many amplifiers are shorted. note 4: the lt6016i/lt6017 are guaranteed functional over the operating temperature range of C40c to 85c. the lt6016h/lt6017h are guaranteed functional over the operating temperature range of C40c to 125c. the lt6016mp/lt6017mp are guaranteed functional over the junction temperature range of C55c to 150c. junction temperatures greater than 125c will promote accelerated aging. the lt6016/lt6017 has a demonstrated typical performance beyond 1000 hours at t j = 150c. note 5: the lt6016i/lt6017i are guaranteed to meet specified performance from C40c to 85c. the lt6016h/lt6017h are guaranteed to meet specified performance from C40c to 125c. the lt6016mp/ lt6017mp are guaranteed to meet specified performance with junction temperature ranging from C55c to 150c. note 6: test accuracy is limited by high speed test equipment repeatability. bench measurements indicate the input offset current in the over-the-top configuration is typically controlled to under 50na at 25c and 150na over temperature. note 7: the reverse supply voltage is tested by pulling 25a/amplifier out of the v + pin while measuring the v + pins voltage with both inputs and v C grounded, verifying v + < C50v.
lt6016/lt6017 8 60167fa typical performance characteristics typical distribution of over-the-top input offset voltage typical distribution of input offset voltage typical distribution of over-the-top input offset voltage voltage offset shift vs lead free ir reflow over-the-top voltage offset shift vs lead free ir reflow voltage offset shift vs lead free ir reflow typical distribution of input offset voltage typical distribution of input offset voltage typical distribution of over-the-top input offset voltage input offset voltage (v) C50 C40 C30 C20 C10 0 number of channels 600 500 400 300 200 100 0 1020304050 60167 g02 v s = 15v v cm = 0v t a = 25c ms8 package 1285 units 2570 channels from two runs input offset voltage (v) C50 C40 C30 C20 C10 0 number of channels 350 300 250 200 150 100 50 0 1020304050 60167 g03 v s = 5v v cm = 5v t a = 25c ms8 package 965 units 1930 channels from two runs input offset voltage (v) C50 C40 C30 C20 C10 0 number of channels 350 300 250 200 150 100 50 0 1020304050 60167 g05 v s = 5v v cm = mid-supply t a = 25c djc22 package 510 units 2040 channels from two runs input offset voltage (v) C100 C80 C60 C40 C20 0 number of channels 500 450 400 350 300 250 200 150 100 50 0 20 40 60 80 100 60167 g06 v s = 5v v cm = 5v t a = 25c djc22 package 510 units 2040 channels from two runs voltage offset shift (v) C20 C15 C10 C5 0 number of channels 18 16 14 12 10 8 6 4 2 0 5 10 15 20 25 60167 g07 24 devices 48 channels ms8 package v s = 5v v cm = mid-supply voltage offset shift (v) C20 C15 C10 C5 0 number of channels 14 12 10 8 6 4 2 0 5 10 15 20 25 60167 g08 24 devices 48 channels ms8 package v s = 5v v cm = 5v input offset voltage (v) C30 C25 C20 C15 C10 C5 0 number of channels 350 400 300 250 200 150 100 50 0 5 10 15 20 25 30 60167 g01 v s = 5v v cm = mid-supply t a = 25c ms8 package 1285 units 2570 channels from two runs input offset voltage (v) C50 C40 C30 C20 C10 0 number of channels 350 300 250 200 150 100 50 0 1020304050 60167 g04 v s = 5v v cm = 76v t a = 25c ms8 package 965 units 1930 channels from two runs voltage offset shift (v) C25 C20 C5 0 0 number of channels 12 10 8 6 4 2 C15 C10 5 10 15 20 25 60167 g09 10 devices 40 channels djc22 package v s = 5v v cm = mid-supply
lt6016/lt6017 9 60167fa typical performance characteristics voltage offset shift vs temperature cycling voltage offset vs temperature over-the-top voltage offset vs temperature voltage offset vs input common mode voltage voltage offset vs supply voltage minimum supply voltage warm-up drift over-the-top warm-up drift voltage offset shift vs thermal cycling time after power on (min) 1 02 C2.5 change in offset voltage (v) 2.5 2.0 1.5 1.0 0.5 0.0 C0.5 C1.0 C1.5 C2.0 35 4 60167 g10 v s = 15v v cm = 0v 5 units, 10 channels ms8 package channel a channel b time after power on (min) 1 02 C2.5 change in offset voltage (v) 2.5 2.0 1.5 1.0 0.5 0.0 C0.5 C1.0 C1.5 C2.0 35 4 60167 g11 v s = 5v v cm = 50v 5 units, 10 channels ms8 package channel a channel b v cm (v) 0.01 C50 input voltage offset (v) 40 50 30 20 10 0 C10 C20 C30 C40 0.1 1 10 60167 g16 100 t a = 25c t a = C45c t a = 125c v s = 5v total supply voltage (v) 5101520 3035 C100 offset voltage (v) 75 100 50 25 0 C25 C50 C75 25 45 40 60167 g17 50 t a = 25c t a = C45c t a = 125c total supply voltage (v) 01 3 C20 change in input offset voltage offset (v) 15 20 10 5 0 C5 C10 C15 24 60167 g18 5 t a = 25c t a = C45c t a = 125c voltage offset shift (v) C25 C20 C5 0 0 number of channels 18 16 14 12 10 8 6 4 2 C15 C10 5 10 15 20 25 60167 g12 four thermal cycles C55c to 130c t a = 25c 20 devices 40 channels ms8 package v s = 5v v cm = mid-supply temperature (c) C25 0 C100 voltage offset shift (v) 100 75 50 25 0 C25 C50 C75 C50 C75 25 50 75 100 125 150 60167 g13 four cycles C55c to 130c v s = 5v, v cm = mid-supply 40 channels measured ms8 package typical channel minimum shift measured worst-case channel maximum shift measured temperature (c) C25 C50 0 25 C150 voltage offset (v) 150 100 50 0 C50 C100 50 150 100 125 75 60167 g14 v s = 5v v cm = mid-supply 5 units, 10 channels ms8 package channel a channel b temperature (c) C25 C50 0 25 C150 voltage offset (v) 150 100 50 0 C50 C100 50 150 100 125 75 60167 g15 v s = 5v v cm = 50v 5 units, 10 channels ms8 package channel a channel b
lt6016/lt6017 10 60167fa typical performance characteristics input bias current vs supply voltage supply current vs supply voltage reverse supply current vs reverse supply voltage noise density vs frequency over-the-top noise density vs frequency 0.1hz to 10hz noise long term stability of five representative units input bias current vs input common mode voltage input bias current vs input common mode voltage supply voltage (v) C60 C15 reverse supply current per amplifier (a) 10 0 5 C5 C10 C50 C40 C30 C20 60167 g24 0 C10 t a = 130c non-inverting op amp configuration +ina, +inb tied to v C t a = C55c t a = 25c t a = 150c time (months) 1 02 C5 change in offset voltage (v) 5 4 3 2 1 0 C1 C2 C3 C4 34 60167 g19 v s = 5v 5 units, 10 channels ms8 package channel a channel b frequency (hz) 1 0 voltage noise density (nv/ hz ) current noise density (pa/ hz ) 60 50 40 30 20 10 0 60 50 40 30 20 10 10 100 1000 60167 g26 v s = 5v v cm = 5v current noise voltage noise time (sec) 0 noise voltage (100nv/div) 26 4810 60167 g27 v s = 2.5v to 25v t a = 25c supply voltage (v) 0 0 supply current per amplifier (a) 600 400 300 500 200 100 10 20 30 40 60167 g23 50 t a = C55c t a = 150c parametric sweep in ~25c increments frequency (hz) 1 0 voltage noise density (nv/ hz hz ) 40 35 30 25 20 15 10 5 0 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 10 100 1000 10k 60167 g25 100k current noise voltage noise input common mode voltage (v) 0.1 C5 input bias current (a) 20 15 10 5 0 110 60167 g20 100 t a = 125c t a = 85c t a = 25c t a = C45c t a = C55c v s = 5v input common mode voltage (v) 0.001 C50 input bias current (na) 25 0 C25 0.01 0.1 1 60167 g21 10 t a = 125c t a = 85c t a = 25c t a = C45c t a = C55c supply voltage (v) 0 C2.5 input bias current (na) 12.5 7.5 5.0 10.0 2.5 0.0 10 20 30 40 60167 g22 50 t a = 125c t a = 85c t a = 25c t a = C45c t a = C55c
lt6016/lt6017 11 60167fa typical performance characteristics closed-loop small signal frequency response gain and phase shift vs frequency gain bandwidth product and phase margin vs supply voltage phase margin vs capacitive load gain-bandwidth vs temperature channel separation vs frequency output impedance vs frequency psrr vs frequency cmrr vs frequency frequency (khz) 0.1 0 cmrr (db) 100 80 60 40 20 1 10 100 1000 60167 g30 v s = 2.5v frequency (khz) 1 C20 gain (db) 50 40 30 20 10 0 C10 10 100 1000 10k 60167 g31 100v/v 10v/v 1v/v capacitive load (pf) 0 30.0 phase margin (deg) 45.0 42.5 40.0 37.5 35.0 32.5 50 100 150 200 250 300 60167 g34 v s = 2.5v i src = 150a i src = 0 frequency (khz) 0.1 60 channel separation (db) 140 130 120 110 100 90 80 70 1 10 100 1000 60167 g36 r load = open v s = 15v r load = 1k frequency (khz) 0 0.01 output impedance () 1000 100 10 1 0.10 1 10 100 1000 60167 g28 10k a v = 100 a v = 10 a v = +1 frequency (khz) 0.1 0 psrr (db) 120 100 80 60 40 20 1 10 100 1000 60167 g29 positive supply negative supply v s = 2.5v frequency (khz) 0.01 C20 gain (db) phase shift (deg) 60 40 20 0 180.0 90.00 112.5 135.0 157.5 0.1 1 10 60167 g32 gain phase v s = 2.5v c load = 20pf temperature (c) C50 2.0 gain-bandwidth (mhz) 4.0 3.5 3.0 2.5 C25 0 25 50 75 100 125 150 60167 g35 v s = 15v v s = 5v total supply voltage (v) 0 3.0 gain bandwidth product (mhz) phase margin (deg) 3.5 3.4 3.3 3.2 3.1 40 60 56 52 48 44 10 20 30 40 50 60167 g33 c load = 30pf gbw pm
lt6016/lt6017 12 60167fa typical performance characteristics small signal transient response large signal transient response output saturation voltage vs input overdrive output saturation voltage (v ol ) vs load current output saturation voltage (v oh ) vs load current open-loop gain settling time to 0.1% vs output step slew rate vs temperature short-circuit vs temperature settling time (s) 2 C5 output step (v) 5 4 0 C2 C3 C4 3 2 1 C1 34567 60167 g37 a v = +1 a v = C1 a v = C1 a v = +1 v s = 2.5v temperature (c) C50 0 slew rate (v/s) 2.0 1.0 0.5 1.5 C25 0 25 50 75 100 125 150 60167 g38 v s = 15v v cm = 0v rising edge falling edge temperature (c) C50 C40 short-circuit current (ma) 40 0 30 10 C10 C30 C20 20 C25 0 25 50 75 100 125 150 60167 g39 v s = 5v sinking sourcing 25mv/div 1s/div 60167 g40 a v = 1v/v v s = 2.5v c load = 20pf input overdrive (mv) 1 output saturation voltage (mv) 1000 100 10 1 10 100 1000 60167 g42 output high output low v s = 2.5v t a = 25c no load output voltage (v) C20 C200 offset voltage (v) 200 150 100 50 0 C50 C100 C150 C10 C15 0 C5 10 15 520 60167 g45 v s = 15v r load = 2k r load = 1m r load = 10k sinking load current (ma) 0.001 1 v ol (mv) 10k 1000 100 10 0.01 0.1 1 10 60167 g43 t a = 125c t a = 25c t a = C45c sourcing load current (ma) 0.001 1 v oh (mv) 10k 1000 100 10 0.01 0.1 1 10 60167 g44 t a = 125c t a = 25c t a = C45c 5v/div 10s/div 60167 g41 a v = 1v/v v s = 15
lt6016/lt6017 13 60167fa applications information supply voltage the positive supply pin of the lt6016/lt6017 should be bypassed with a small capacitor (typically 0.1f) as close to the supply pins as possible. when driving heavy loads an additional 4.7f electrolytic capacitor should be added. when using split supplies, the same is true for the v C supply pin. the lt6017 consists of two dual amplifier dice assembled in a single dfn package which share a common substrate (v C ). while the v C pins of the quad (pins 5 and 7) must always be tied together and to the exposed pad underneath, the v + power supply pins (pins 16 and 18) may be sup- plied independently. the b and c channel amplifiers are supplied through v + by pin 16, and the a and d channel amplifiers are supplied by pin 18. if pin 16 and pin 18 are not tied together and are biased independently, each v + pin should have their own dedicated supply bypass to ground. shutdown while there are no dedicated shutdown pins for the lt6016/ lt6017, the amplifiers can effectively be shut down into a low power state by removing v + . in this condition the input bias current is typically less than 1na with the inputs biased between v C and 76v above v C , and if the inputs are taken below v C , they appear as a diode in series with 1k of resistance. the output may be pulled up to 50v above the v + power supply in this condition (see figure 1). pulling the output pin below v C will produce unlimited current and can damage the part. reverse battery the lt6016/lt6017 are protected against reverse battery voltages up to 50v. in the event a reverse battery condi- tion occurs, the supply current is typically less than 5a (assuming the inputs are biased within a diode drop from v C ). for typical single supply applications with ground re- ferred loads and feedback networks, no other precautions are required. if the reverse battery condition results in a negative voltage at the input pins, the current into the pin should be limited by an external resistor to less than 10ma. inputs referring to the simplified schematic, the lt6016/lt6017 has two input stages: a common emitter differential input stage consisting of pnp transistors q1 and q2 which operate when the inputs are biased between v C and 1.5v below v + , and a common base input stage consisting of pnp transistors q3 to q6 which operate when the common mode input is biased greater than v + C1.5v. this results in two distinct operating regions as shown in figure 2. for common mode input voltages approximately 1.5v or more below the v + supply (q1 and q2 active), the com- mon emitter pnp input stage is active and the input bias current is typically under 2na. when the common mode input is within approximately 1v of the v + supply or higher figure 1. lt6016/lt6017 fault tolerant conditions inputs driven above supply tolerant 5v C + ok! 80v + reverse battery tolerant C50v C + ok! inputs driven below ground tolerant 25v transient 5v C + ok! large differential input voltage tolerant 5v C + ok! 80v + output driven above the v + supply (in shutdown) tolerant 0v C + ok! 60167 f01 50v + C +
lt6016/lt6017 14 60167fa applications information (over-the-top operation), q9 begins to turn on diverting bias current away from the common emitter differential input pair to the current mirror consisting of q11 and q12. the current from q12 will bias the common base differential input pair consisting of q3 to q6. because the over-the-top input pair is operating in a common base configuration, the input bias current will increase to about, 14a. both input stages have their voltage offsets trimmed tightly and are specified in the electrical characteristics table. the inputs are protected against temporary excursions to as much as 25v below v C by internal 1k resistor in series with each input and a diode from the input to the negative supply. adding additional external series resistance will extend the protection beyond 25v below v C . the input stage of the lt6016/lt6017 incorporates phase reversal protection to prevent the output from phase reversing for inputs below v C . there are no clamping diodes between the inputs. the inputs may be over-driven differentially to 80v without damage, or without drawing appreciable input current. figure 1 summarizes the kind of faults that may be applied to the lt6016/lt6017 without damage. over-the-top operation considerations when the input common mode of the lt6016/lt6017 is biased near or above the v + supply, the amplifier is said to be operating in the over-the-top configuration. the differential input pair which control amplifier operation is common base pair q3 to q6 (refer to the simplified schematic). if the input common mode is biased between v C and approximately 1.5v below v + , the amplifier is said to be operating in the normal configuration. the differential input pair which control amplifier operation is common emitter pair q1 and q2. a plot of the over-the-top transition region vs temperature (the region between normal operation and over-the-top operation) on a 5v single supply is shown in figure 2. some implications should be understood about over- the-top operation. the first, and most obvious is the input bias currents change from under 2na in normal operation to 14a in over-the-top operation as the input stage transitions from common emitter to common base. even though the over-the-top input bias currents run around 14 a, they are very well matched and their offset is typically under 100na. the second and more subtle change to amplifier operation is the differential input impedance which decreases from 1m in normal operation, to approximately 3.7k in over-the-top operation (specified as r in in the electrical characteristics table). this resistance appears across the summing nodes in over-the-top operation and is due to the common base input stage configuration. its value is easily derived from the specified input bias current flowing into the op amp inputs and is equal to 2 ? k ? t/(q ? ib) (k-boltzmanns constant, t C operating temperature, ib-operating input bias current of the amplifier in the over-the-top region). and because the inputs are biased proportional to absolute temperature, it is relatively constant with temperature. the user may think this effective resistance is relatively harmless because it appears across the summing nodes which are forced figure 2. lt6016/lt6017 over-the-top transition region vs temperature temperature (c) C50 v cm (v) 5.0 4.5 3.5 2.5 4.0 3.0 2.0 1.5 1.0 0.5 0 50 0 100 125 60167 f02 150 25 C25 75 v s = 5v transistion region typical common mode voltage for onset of over-the-top operation typical common mode voltage where over-the-top operation fully on
lt6016/lt6017 15 60167fa to 0v differential by feedback action of the amplifier. however, depending on the configuration of the feedback around the amplifier, this input resistance can boost noise gain, lower overall amplifier loop gain and closed loop bandwidth, raise output noise, with one benevolent effect in increasing amplifier stability. in the normal mode of operation (where v C < v cm < v + C1.5v), r in is typically large compared to the value of the input resistor used, and r in can be ignored (refer to figure 3). in this case the noise gain is defined by the equation: noise gain 5 1 + r f r i however, when the amplifier transitions into over-the-top mode with the input common mode biased near or above the the v + supply, r in should be considered. the noise gain of the amplifier changes to: noise gain = 1 + r f r i || r in + r i ||r f () likewise the closed loop bandwidth of the amplifier will change going from normal mode operation to over-the- top operation: normal mode: bw closed < loop 5 gbw 1 + r f r i over-the-top mode: bw closed < loop 5 gbw 1 + r f r i || r in + r i ||r f () and output noise is negatively impacted going from normal mode to over-the-top: normal mode: (neglecting resistor noise) e no 5 e ni ?1 + r f r i over-the-top mode: (neglecting resistor noise) e no 5 e ni ?1 + r f r i || r in + r i ||r f () 2 2 | output the output of the lt6016/lt6017 can swing within a schottky diode drop (~0.4v) of the v + supply, and within 5mv of the negative supply with no load. the output is capable of sourcing and sinking approximately 25ma. the lt6016/lt6017 are internally compensated to drive at least 200pf of capacitance under any output loading conditions. for larger capacitive loads, a 0.22f capaci- tor in series with a 150 resistor between the output and ground will compensate these amplifiers to drive capacitive loads greater than 200pf. applications information while it is true that the dc closed loop gain will remain mostly unaffected (= r f r i ), the loop gain of the amplifier has decreased from a ol 1 + r f r i to a ol 1 + r f r i || r in + r i ||r f () figure 3. difference amplifier configured for both normal and over-the-top operation + C 5v 1/2 lt6016 v in v incm r i r f v out r f r i r in 60167 f03
lt6016/lt6017 16 60167fa distortion there are two main contributors of distortion in op amps: output crossover distortion as the output transitions from sourcing to sinking current and distortion caused by nonlinear common mode rejection. if the op amp is operating in an inverting configuration there is no com- mon mode induced distortion. if the op amp is operating in the noninverting configuration within the normal input common mode range (v C to v + C1.5v) the cmrr is very good, typically over 120db. when the lt6016 transitions input stages going from the normal input stage to the over-the-top input stage or vice-versa, there will be a significant degradation in linearity due to the change in input circuitry. lower load resistance increases distortion due to a net decrease in loop gain, and greater voltage swings internal to the amp necessary to drive the load, but has no effect on the input stage transition distortion. the lowest distor- tion can be achieved with the lt6016/lt6017 sourcing in class-a operation in an inverting configuration, with the input common mode biased mid-way between the supplies. power dissipation considerations because of the ability of the lt6016/lt6017 to operate on power supplies up to 25v and to drive heavy loads, there is a need to ensure the die junction temperature does not exceed 150c. the lt6016 is housed in an 8-lead msop package ( e ja = 273c/w). the lt6017 is housed in a 22 pin leadless dfn package (djc22, e ja = 31.8c/w). in general, the die junction temperature (t j ) can be esti- mated from the ambient temperature t a , and the device power dissipation p d : t j = t a + p d ? e ja the power dissipation in the ic is a function of supply voltage and load resistance. for a given supply voltage, the worst-case power dissipation p d(max) occurs at the maximum supply current with the output voltage at half of either supply voltage (or the maximum swing is less than one-half the supply voltage). p d(max) is given by: p d(max) = (v s ? i s(max) ) + (v s /2) 2 /r load example: an lt6016 in a msop package mounted on a pc board has a thermal resistance of 273c/w. operating on 25v supplies with both amplifiers simultaneously driving 2.5k loads, the worst-case ic power dissipation for the given load occurs when driving 12.5v peak and is given by: p d(max) = 2 ? 50 ? 0.6ma + 2 ? (12.5) 2 /2500 = 0.185w with a thermal resistance of 273c/w, the die temperature will experience approximately a 50c rise above ambient. this implies the maximum ambient temperate the lt6016 should ever operate under the assumed conditions: t a = 150c C 50c = 100c to operate to higher ambient temperatures, use two chan- nels of the lt6017 quad which has lower thermal resistance e ja = 31.8c/w, and an exposed pad which may be soldered down to a copper plane (connected to v C ) to further lower the thermal resistance below e ja = 31.8c/w. applications information
lt6016/lt6017 17 60167fa simplified schematic 60167 ss q10 pnp q9 pnp q6 pnp q5 pnp q2 pnp q1 pnp q3 pnp q4 pnp q12 npn q11 npn r5 40k 5a i2 v + v C Cin r3 6k r4 6k +in d4 d1 d2 r1, 1k r2, 1k 16a i1 8a i3 8a out m2 pmos m1 pmos i4 q7 npn q8 npn q13 npn p n class ab adjust d3
lt6016/lt6017 18 60167fa typical applications gain of 100 high voltage difference amplifier with C5v/75v common mode range C + 5v C5v 1k 100k 97.6k cmrr adjust 5k 1k v out t7 in 1/2 lt6016 v in v cm 60167 ta02 + C + C
lt6016/lt6017 19 60167fa package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f)
lt6016/lt6017 20 60167fa package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package note: 1. dimensions are in millimeters 2. apply solder mask to areas that are not soldered 3. drawing is not to scale 0.40 0.05 pin #1 notch r0.30 typ or 0.25mm w 45 chamfer bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.10 typ 1 22 12 11 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (djc) dfn 0605 6.00 0.10 (2 sides) 0.25 0.05 0.889 0.889 0.50 bsc 5.35 0.10 (2 sides) r = 0.10 recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.50 bsc 5.35 0.05 (2 sides) 0.889 0.889 djc package 22-lead plastic dfn (6mm w 3mm) (reference ltc dwg # 05-08-1714 rev ?)
lt6016/lt6017 21 60167fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 01/13 corrected block diagram q7 and q8 17
lt6016/lt6017 22 60167fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0113 rev a ? printed in usa related parts typical application part number description comments lt1490a/lt1491a dual and quad micropower rail-to-rail input and output op amp over-the-top inputs, 50a/amplifier, reverse battery protection to 18v lt1638/lt1639 1.2mhz, 0.4v/s over-the-top rail-to-rail input and output op amp over-the-top inputs, 230a/amplifier, 1.2mhz gbw, 0.4v/s slew rate lt1494/lt1495/lt1496 1.5a max, single, dual, and quad, over-the-top precision rail-to-rail input and output op amps over-the-top inputs, 1.5a/amplifier, 375v voltage offset lt1112/lt1114 dual/quad low power precision, pa input op amp 60v offset voltage, 400 a/amplifier lt1013/LT1014 dual/quad precision op amp 150v offset voltage, 500 a/amplifier extended supply current boosted gain of three amplifier drives 100 load to 30v, with 600ma current limit C + 35v C35v 1k 604 1 1/2w 1k 820pf 35v C35v 1k 0.1f 1/2 lt6016 v out = 30v 24v z * 24v z * 2 1n4148 or equivalent 60167 ta03 47nf q1 q2 47nf 10nf *zener diodes: central semi cmz5934 q1, q2: on-semi d44vh10 npn, d45vh10 pnp with heat sink **both halves of lt6016 on same supply C + 1/2 lt6016** 330 10k v in 1k 20k 100k 330pf

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